The present application is related to U.S. application Ser. No. 09/255,926 filed on an even date herewith, by Duane Abbey, entitled xe2x80x9cData Pattern Correlatorxe2x80x9d.
The present invention relates generally to communication systems. More particularly, the present invention relates to a phase processor for a data pattern recognizer. The phase processor generates a synchronization signal for adjusting a data acquisition clock.
Data pattern recognizers or correlators are generally utilized in various communication systems to determine if a particular pattern has been received. Once the data pattern is recognized, the correlator provides a time registration or synchronization signal. The synchronization signal is utilized to coordinate the reception of data or information relative to the particular pattern.
Correlators, such as, binary correlators, are utilized for A/J (spread spectrum) message and other data message synchronization. In an exemplary radio system application, a data pattern correlator analyzes the received radio signal to determine if a particular data pattern is present. The data pattern can be comprised of a number of symbols, such as, digital bits, or other indicators, provided in series on a particular radio channel. After the radio system determines that the particular pattern is present, it can then receive further information, such as, data, voice, or other symbols, in accordance with a synchronized communication technique. The data pattern and information can be modulated on the radio signal via any suitable technique, including amplitude modulation, phase modulation, frequency modulation, quadrature amplitude modulation, frequency shift key modulation, or other technique.
Conventional data pattern recognizers have utilized match-filtering techniques which can be susceptible to false pattern recognition due to noise, especially when the data pattern is short. Typically, conventional data pattern recognizers or correlators have increased the size of the data pattern to decrease the occurrence of false pattern recognition. However, increasing the data pattern size presents other problems with pattern recognition performance. Longer data patterns require increased hardware overhead and communication time for recognition. More communication time adversely affects minimum signal dwell times (maximum hop rates) message access times, and message turn-around time periods. In addition, longer correlators become susceptible to missed recognitions due to symbol rate differences between the received signal and the correlator symbol rate clock.
Conventional data pattern recognizers or correlators oversample the incoming signal and compare only one sample of the incoming signal to each symbol in the data pattern (e.g., samples are compared to symbols on a one-to-one basis). With this conventional approach, the only way to improve performance at a constant false recognition rate is to increase the number of characters in the data pattern. As stated above, such a solution has significant disadvantages.
In a conventional system, if all samples of the oversampled incoming signal are compared to each symbol (e.g., multiple samples per symbol or character), any performance gained is reduced by inaccuracies due to channel non-linearities and to doppler shift (difference between the received symbol rate and the correlator""s symbol rate). Therefore, comparing all of the samples to each symbol also has significant disadvantages.
Heretofore, current time registration techniques also suffer in deficiencies and accuracy (generally from xc2x1xc2xdcharacter or more), due to software processing time, character uncertainty, and low accuracy correlation phase sorting. Further, several data characters can be lost immediately after the pattern recognition due to the slow response time of current correlator techniques.
Thus, there is a need to improve data pattern recognition performance for a given number of pattern characters and maintain a low constant false match rate due to noise. Further, there is a need to perform data correlation utilizing multiple samples per character. Further still, there is a need for greater synchronization reliability in communication applications. Further still, there is a need for an accurate, low cost phase processor for a data correlator.
The present invention relates to a status processor for generating a synchronization signal. The synchronization signal synchronizes a data sampling clock. The status processor includes a matched status input and a control circuit. The matched status input receives a matched status signal indicating a pattern match of at least one phase of an incoming signal to a data pattern. The control circuit is coupled to the matched status input and includes a counter circuit and a logic circuit. The counter circuit performs a count operation in response to a counter signal generally having a frequency of at least two times the phase rate (sample rate) of the data symbols and in response to the matched status signal. The logic circuit generates the synchronization signal in response to the count operation to adjust the data sampling clock in accordance with the match status signal.
The present invention further relates to a status processor for use in a data pattern correlator. The data pattern correlator provides a matched status signal indicating a pattern match of at least one phase of an incoming signal to a data pattern. The incoming signal is provided in accordance with a data sampling clock. The status processor includes a counter circuit and a logic circuit. The counter circuit performs a count operation in response to a counter signal generally having a frequency of at least two times the phase rate (sample rate) of the data symbols and in response to the matched status signal. The logic circuit is coupled to the counter circuit and controls the counter circuit. The logic circuit generates the synchronization signal in response to the count operation to adjust the sampling clock in accordance with the match status signal.
The present invention still further relates to a status processor for use in a data pattern correlator. The data pattern correlator provides a matched status signal indicating a pattern match of at least one phase of an incoming signal to a data pattern. The incoming signal is provided in accordance with a data sampling clock. The status processor includes a counter means for performing a count operation and a logic means for generating the synchronization signal. The count operation. is performed in response to a counter signal generally having a frequency of at least 2 times the phase rate (sample rate) of the data symbols and in response to the match status signal. The synchronization signal is generated in response to the count operation to adjust the data sampling clock in accordance with the match status signal.